1. Field of the Invention
The present invention relates to a comparison device and an analog-to-digital converter using the same adaptive background calibration scheme, and more particularly, to a device with adaptive background calibration scheme that can eliminate an offset voltage of the comparators.
2. Description of Related Art
With the continuous increase of communication network bandwidth, a conversion rate of a front-end analog-to-digital converter (ADC) must be increased for the requirements of an overall system. A flash ADC is the most popular architecture to implement high sampling rate ADC. FIG. 1 is a circuit diagram of the flash ADC. Referring to FIG. 1, the flash ADC 100 consists of 2N−1 comparators for comparing the sampled signal Vi with different reference voltages Vr, and also consists of encoder 110 for performing the bubble prevention and converting the thermal codes to the binary codes. The intrinsic limitations of the flash ADC 100 are the process variation of a reference ladder resistance, the mismatch among the 2N−1 signal paths, and the threshold mismatch among the comparators.
The process variation of a reference ladder resistance is not a big problem at the moderate accuracy level, e.g. 6-8 bit. The mismatch problem of the signal propagation delay and the synchronization problem of the strobe clock signal can be solved by putting a front-end dedicated track-and-hold amplifier before the comparator array. A comparator includes a preamplifier and a latch. The straightforward way to overcome the threshold mismatch problem among the comparators is to enlarge the size of the preamplifiers for getting enough accumulative gain before the latches and reducing the influence of the latches' offset voltage. However, the ADC power efficiency is lowered because of the strong tradeoff among accuracy, speed, and power consumption.
FIG. 2 is a circuit diagram of background comparator offset calibration technique for flash ADC converters disclosed in U.S. Pat. No. 7,064,693. Referring to FIG. 2, the random chopping comparator includes a comparator 210 together with two choppers CHP1 and CHP2, wherein the offset voltage Vos of the comparator is unknown. The choppers CHP1 and CHP2 has two states: in forward states, the input signals Vi and Vr are connected to the input terminals of the comparator 210, and the digital signal Di outputted from the comparator serves as an output signal De; in the reversed state, the input signal Vi and Vr are reversed and connected to the input terminals of the comparator 210, and the digital signal Di outputted from the comparator is inversed and serves as an output signal Dc. The choppers CHP1 and CHP2 are controlled by the random sequence q[k], which the probability of generating a forward signal or a reversed signal is 50%.
A correlated variable “U” is defined and utilized to calibrate the offset voltage Vos. When the output signal De is “1” and the q[k] is “forward”, the correlated variable “U” is “+1”. When the output signal Dc is “1” and the q[k] is “reverse”, the correlated variable “U” is “−1”. When the output signal Dc is “0”, the correlated variable “U” is “0”. By cooperating with the choppers CHP1 and CHP2, the calibration processor 220 accumulates the correlated variable “U”, wherein the accumulation of the correlated variable “U” reflects the value of the offset voltage Vos and the polarity of the offset voltage Vos can be estimated. By this way, the calibration processor 220 determines to increase or decrease the offset voltage Vos with a small fixed amount for calibrating the offset voltage Vos.
The aforementioned calibration technique is a background digital calibration, and requires less analog overhead. However, an input signal with invariant statistic is required, and the settling behavior is slow since the calibration technique is statistics-based. Therefore, it is an inevitable trend to develop a high-speed ADC with calibration capability to decrease power consumption.